As it is well known, electrically erasable non volatile memory cells are nowadays widespread in several applications. Among them the cells of the EEPROM type show a particular importance, both for their capacity to be erased per single word and programmed per single bit, and for the extremely reduced current consumption in the read and modify modes (erasing/programming).
The use of EEPROM memories is nowadays particularly widespread for the applications onto electronic devices such as the so called Smart Cards, where these types of memories are used with great success.
Actually, the need of scaling down the physical dimension of these devices so as to reduce the costs and to be more competitive in the market of semiconductors, has pushed the physical dimension of the EEPROM cells to such a point as to lead to the physical limit the possibility of further reducing these dimensions, the malfunctioning of the devices themselves being the price.
This is essentially due to the physical principle upon which the operation of an EEPROM cell is based in the modify mode, which consists of applying high electrical fields (˜10-12 MV/cm) onto the MOS transistor which realizes the cell and which has a thin dielectric capacitor structure (˜7 nm) aimed at obtaining significant Fowler-Nordheim currents (˜60 pA/cell) and at accumulating positive or negative charge on the floating gate terminal of the cell itself. An EEPROM memory cell in fact comprises, in a known way, a floating gate transistor, this floating gate region being realized above a tunnel oxide and overhung by a control gate electrode.
The Fowler-Nordheim mechanism requires, for the charge transfer, high voltage values, in the order of 12V, which cannot be scaled down due to the fact that the thickness of the cell tunnel oxide cannot be in turn reduced below a certain limit, and this is due to considerations linked to the reliability of the cell itself (the so called endurance with respect to programming/erasing cycles and charge retention).
The fact of having to impose these high voltage values particularly limits the possibility of scaling down the physical dimensions of the cell selector, i.e. a selection transistor associated with each EEPROM memory cell whose aim is that of insulating the cell when the cell is not selected and of allowing the passage of the biasing voltages on the modification of the cell state.
It is thus a high voltage (HV) transistor on whose control gate voltage up to 15V can be applied necessary to allow the passage of 12V on the drain terminal of the memory cell associated therewith, in turn realized by a floating gate transistor also called sensing transistor.
The EEPROM memory cells currently used in the industry of semiconductors for high density applications, such as the use on Smart Card devices, have a structure with a double polysilicon or poly layer and a cell selection transistor. The cells are designed so as to form words of a certain number of bits (for example 8 bits or 32 bits) which depend on the used parallelism. The control gate of these cells is then accessed by means of a corresponding word selection transistor (also called byte switch) which allows biasing the control gates of these cells both in reading and in erasing, or to insulate the same from the biasing voltages in case these cells are not selected.
A memory architecture including a matrix of cells of the EEPROM type realized according to the prior art is schematically shown in FIG. 1 and globally indicated with a 1.
This memory architecture 1 comprises a matrix 2 of memory cells 3 of the EEPROM type, each comprising one sensing or cell transistor MC, i.e. a floating gate transistor constituting the real memory cell, and a cell selection transistor TS.
The EEPROM cells are organized in a matrix, in the example shown in a parallel architecture comprising an array of w bits.
The matrix 2 of cells is connected to a switch portion 4 comprising a plurality of byte switches 5. The byte switch is an element which allows the biasing of the control gate terminals of the memory cells in the various modify and read operations. The switch portion 4 is repeated symmetrically for the successive portions of the matrix 2.
The memory architecture 1 shows in fact a symmetrical structure with respect to a source line SL shared by the entire matrix 2.
In particular, the cell transistors MC belonging to a same word 6 have first conduction terminals, in particular drain terminals, connected to respective selection transistors TS, second conduction transistors, in particular source terminals connected to each other and to the source line SL and control or gate terminals connected to each other and to a respective byte switch 5 of the switch portion 4.
The byte switches 5 have first conduction terminals, in particular source terminals, connected to control gate terminals of the cell transistors MC of a same word 6, second conduction terminals, in particular drain terminals, connected to each other and to a control gate line CGT and control or gate terminals connected to the control or gate terminals shared by the selection transistors TS of the word 6 as well as to respective word lines WL. In this way, all the memory cells 3 belonging to a same word 6 are driven by a same byte switch 5.
Finally, the selection transistors TS have first conduction terminals, in particular drain terminal, connected to respective bit lines BL, second conduction terminals, in particular source terminals, connected to the cell transistors MC and control or gate terminals connected to the word lines WL.
In the architecture 1 as shown, the various programming, erasing and reading operations occur by using particular values for the signals applied onto the lines connected to the terminals of the cell MC and select TS transistors of the memory cells 3, selected (sel) or non selected (non sel), according to what is shown in the following table 1.
TABLE 1ProgrammingReadingLineErasing operationoperationoperationCGT selVe0 VVr1CGT non selFLOAT0 V0 VBL selFLOATVpVr2BL non selFLOATFLOATFLOATWL selVe + Vth bsw(Ve)Vp + Vth sel(Vp)Vr3WL non sel0 V0 V0 VSL0 VFLOAT0 Vbeing:
CGT, BL, WL and SL the control gate, bit, word and source lines respectively;
Ve, Vp erase and program voltage values, respectively;
Vth bsw(Ve) and Vth sel(Vp) threshold voltage values of the byte switch and selection transistors, under conditions of body effect equal to the erase and program voltages, respectively; and
Vr1, Vr2 e Vr3 read voltage values, normally equal to about 1V, 0.8V and 5V.
The word FLOAT also indicates when no biasing voltage is applied onto the corresponding line.
During the programming operation electrons are extracted from the floating gate until a first threshold voltage is obtained lower than a first level UV (state devoid of charge) suitable for coding a first logic level, or logic “1”. During the erasing operation, there occurs, in a dual way, an injection of electrons into the floating gate until a second threshold voltage is obtained higher than this first level UV to code a second logic level, or logic “0”.
As it is evident from the biasing voltages at stake, in the modifying operations of the charge contained in the floating gate of the cells (programming and erasing), the stress condition to which the various terminals of the cells are subjected are such as to impose a strong limitation to the possibility of scaling down the physical dimensions of the same.
In particular, it is remarked that:
1) It is necessary to maintain the right distance between the active areas of the cell and selection transistors, to allow an efficient insulation between the bit lines against the field parasite transistor (which has a voltage value equal to the word line voltage (i.e. Ve+Vthsel(Ve) applied onto its gate terminal).
2) The minimum length of the selection transistor which serves as cell selector cannot be reduced below a certain limit due to the fact that, during the programming operations, on the drain terminal of this selection transistor a voltage must be applied equal to the programming voltage Vp, and the selection transistor must however ensure the insulation of cells which do not have to be programmed. Under these conditions there has not to be any current induced by high voltages onto its drain terminal.
3) The width of the selection transistor can be reduced only within certain limits, to avoid a significant degradation of the gain of the transistor itself and a subsequent strong limitation of the current necessary in the reading operations.
4) The voltages applied onto the lines of the memory cells should however be maintained around a value equal to ˜12V to ensure a correct programming of the cells, since it is not possible to reduce the thickness of their tunnel oxide not to go below the limit imposed by the requisites linked to the reliability of the memory.
It can thus be understood how these constraints impose a physical limit to the possibility of scaling down the minimum dimensions of an EEPROM cell of a memory architecture realized according to the prior art.